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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

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Beschreibung

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA...

Beschreibung

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Produktdetails

Einband

Gebundene Ausgabe
Erscheinungsdatum

21.10.2011
Abbildungen

XXII, 170 p.
Verlag Springer Us

Produktdetails

Einband

Gebundene Ausgabe
Erscheinungsdatum

21.10.2011
Abbildungen

XXII, 170 p.
Verlag Springer Us
Seitenzahl

170
Maße (L/B/H)

24,1/16/1,6 cm
Gewicht

407 g
Sprache

Englisch
ISBN

978-1-4614-0871-0
Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: ProductSafety@springernature.com

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  • Produktbild: Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
  • Produktbild: Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

  • Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.